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| www..com STE101P 10/100 Fast ethernet 3.3 V transceiver Features IEEE802.3u 100Base-TX and IEEE802.3 and 10Base-T transceiver Support for IEEE802.3x flow control MII /RMII / SMII interface Auto MDIX supported Provides Full-duplex operation on both 100Mbps and 10Mbps modes Provides MLT-3 transceiver with DC restoration for Base-line wander compensation Provides loop-back modes for diagnostics Supports external transformer with turn ratio 1.414:1 on Tx/Rx side. Five LED display for operating mode and functionality signalling Operation from single 3.3V supply High Cable ESD tolerance Standard 64-pin QFP package pinout Industrial temperature compliant Self termination transceiver for external components and power saving Power dissipation < 200mW TQFP64 10 x 10 Description The STE101P is a high performance Fast Ethernet physical layer interface for 10Base-T and 100Base-TX application. It was designed with advanced CMOS technology to provide MII, RMII and SMII interfaces for easy attachment to 10/100 Media Access Controllers 100Base-TX of IEEE802.3u and 10Base-T of IEEE802.3 The STE101P supports both half-duplex and fullduplex operation at 10 and 100 Mbps operation. Its operating mode can be set using auto negotiation, parallel detection or manual control. It also allows for the support of auto-negotiation functions for speed and duplex detection. The Automatic MDI / MDIX feature compensates for using a cross over cable. With Auto MDIX, the STE101P automatically detects what is on the other end of the network cable and switches the TX & RX pins accordingly. Applications Switches/routers/hubs NIC adapters Game consoles VoIP gateways/phones Network printers DTVs/DVD-Rs September 2006 Rev 1 1/53 www.st.com 1 DataSheet 4 U .com www..com Contents STE101P Contents 1 2 System and block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 2.2 2.3 Physical layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 LED display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 4 5 Pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Hardware control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1 5.2 Operating configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 LED / PHY address interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6 Registers and descriptors description . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.1 6.2 Register list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7 Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 100Base-TX transmit operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 100Base-TX receive operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10Base-T transmit operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 10Base-T receive operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Loop-back operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Full duplex and half duplex operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Auto-negotiation operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Power down operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 LED display operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Preamble suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Remote fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Transmit isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2/53 DataSheet 4 U .com www..com STE101P Contents 7.14 7.15 7.16 Automatic MDI / MDIX feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 RMII interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 SMII interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8 9 10 11 Electrical specifications and timings . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3/53 DataSheet 4 U .com www..com List of tables STE101P List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 CFG decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 List of registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PR00 [0d00, 0x00]: MII control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PR01 [0d01, 0x01]: MII status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PR02 [0d02, 0x02]: PHY Identifier (HI) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 PR03 [0d03, 0x03]: PHY Identifier (LO) register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 PR04 [0d04, 0x04]: Auto negotiation advertisement register . . . . . . . . . . . . . . . . . . . . . . . 19 PR05 [0d05, 0x05]: Auto negotiation link partner ability register . . . . . . . . . . . . . . . . . . . . 20 PR06 [0d06, 0x06]: Auto negotiation expansion register . . . . . . . . . . . . . . . . . . . . . . . . . . 21 PR07 (0d07, 0x07): Auto negotiation next page transmit register . . . . . . . . . . . . . . . . . . . 21 PR08 [0d08, 0x08]: Auto negotiation link partner next page transmit reg. . . . . . . . . . . . . . 22 PR10 [0d16, 0x10]: 100BaseTX auxiliary control register . . . . . . . . . . . . . . . . . . . . . . . . . 22 PR11 [0d17, 0x11]: 100BaseTX Auxiliary Status Register . . . . . . . . . . . . . . . . . . . . . . . . . 23 PR12 [0d18, 0x12]: Interrupt enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 PR13 [0d19, 0x13]: 100BaseTX control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 PR14 [0d20, 0x14]: XCVR Mode control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 PR18 [0d24, 0x18]: Auxiliary control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 PR19 [0d25, 0x19]: Auxiliary status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 PR1A[0d26, 0x1A]: Interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 PR1B [0d27, 0x1B]: Auxiliary mode 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 PR1C[0d28, 0x1C]: 10Base-T error and general status register . . . . . . . . . . . . . . . . . . . . 30 PR1D[0d29, 0x1D]: control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 PR1E[0d30, 0x1E]: Auxiliary PHY register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 PR1F[0d31, 0x1F]: Shadow register enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 RS18 [0d24, 0x18]: 100BaseTX Disconnect Counter Register . . . . . . . . . . . . . . . . . . . . . 33 RS1B [0d27, 0x1B]: MISC Status/error/test register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 RS1C[0d28, 0x1C]: Auxiliary status 3 - FIFO status register . . . . . . . . . . . . . . . . . . . . . . . 35 RS1D [0d29, 0x1D]: FIFO control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 RS1E [0d30, 0x1E]: Packet counter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 General DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 X1 and NLP timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Fast link pulse (FLP) AC timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Mll management and 100Base-TX transmitter AC timing specifications . . . . . . . . . . . . . . 45 Mll receive and 100Base-TX AC timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 MII transmit and 100Base-TX transmitter AC timing specifications . . . . . . . . . . . . . . . . . . 47 RMII AC timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 SMII AC timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 TQFP 64L/Body 10 x 10 x 1.40 mm / footprint 1.00 mm . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4/53 DataSheet 4 U .com www..com STE101P List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. System diagram of the STE101P application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 LED connection for Logic level 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 LED connection for Logic level 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Transmit isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Normal link pulse timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Fast link pulse timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 MII management clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 MII receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 MII transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 RMII transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 RMII receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 SMII transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 SMII receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 TQFP 64 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5/53 DataSheet 4 U .com www..com System and block diagrams STE101P 1 System and block diagrams Figure 1. System diagram of the STE101P application Serial EEPROM PCI interface LEDs MAC device STE101P Transformer RJ-45 Boot ROM 25 MHz crystal Figure 2. LEDS Block diagram LEDS 100Mb/s TX_CLK TXD[3:0] TX_ER TX_EN 4B/5B TX Channel Scrambler Parallel to Serial NRZ To NRZI Encoder Binary To MLT3 Encoder TRANSMITTER 10/100 10 TX Filter TXP TXN 10Mb/s MDIO Interface / Controller MDC MII / RMII / SMII Interface Serial Management NRZ To Manchester Encoder Link Pulse Generator /RMII/SMII REGISTERS Auto Negotiation Loopback Clock Generation System Clock RXD[3:0] RX_ER RX_DV MII RX Channel 100Mb/s 4B/5B RX_CLK Descrambler Code Align Binary To MLT3 Decoder Adaptive Equalization BaseLine Wander Serial to Parallel NRZI To NRZ Decoder Clock Recovery RECEIVER 10/100 RXP RXN COL HW CRS 10Mb/s configuration pins HW Config Power Down NRZ To Manchester Encoder Link Pulse Detector 10 TX Filter Clock Recovery SMART Squelch 6/53 DataSheet 4 U .com www..com STE101P Features 2 2.1 Features Physical layer Integrates the whole physical layer functions of 100Base-TX and 10Base-T Provides full-duplex operation on both 100Mbps and 10Mbps modes Provides auto-negotiation (NWAY) function of full/half duplex operation for both 10 and 100 Mbps Provides MLT-3 transceiver with DC restoration for base-line wander compensation Provides transmit wave-shaper, receive filters, and adaptive equalizer Provides loop-back modes for diagnostic Builds in stream cipher scrambler/ de-scrambler and 4B/5B encoder/decoder Supports external transmit transformer with turn ratio 1.414:1 Supports external receive transformer with turn ratio 1.414:1 2.2 LED display The LED display, consists of five LEDs having the following characteristics: 10 Mbps speed LED: 10Mbps(on) or 100Mbps(off) 100 Mbps speed LED: 100Mbps(on) or 10Mbps(off) TX/RX activity LED: Blinks at 10Hz when receiving, but not colliding Link LED: On when a good link is detected, blinks when there is TX or RX activity Full duplex / collision LED: ON during full duplex operation. Blinks at 20Hz to indicate a collision 2.3 Package Standard 64-pin QFP package pinout 7/53 DataSheet 4 U .com www..com Pin assignment STE101P 3 Pin assignment Figure 3. Pin assignment 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 tx_clk tx_er / txd4 rx_er / rxd4 gnd rx_clk mdint crs col txd3 txd2 txd1 txd0 tx_en cfg1 dvdd cfg0 mf4 mf3 mf2 mf1 mf0 fde gnda nc vcca gnda x2 x1 vcca gnda iref vcca 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 rx_dv rxd0 rxd1 dvdd rxd2 rxd3 mdc mdio gnd ovdd ledr10 ledtr ledl ledc leds test_se gnda gnd test pwrdwn 8/53 DataSheet 4 U .com reset rip mdix_dis cf2 sclock rxn rxp gnda txp nc txn vcca www..com STE101P Pin description 4 Table 1. Pin No. Pin description Pin description Name Type Description Data interface Transmit Coding Error. The MAC asserts this input when an error has occurred in the transmit data stream. When the STE101P is operating at 100 Mbps, the STE101P responds by sending invalid code symbols on the line. In Symbol (5B) Mode this pin functions as txd4. Transmit Data. The Media Access Controller (MAC) drives data to the STE101P using these inputs. txd4 is monitored only in Symbol (5B) Mode. These signals must be synchronized to the tx_clk. *txd0 = MII/RMII/SMII tx data *txd1 = MII/RMII tx data *txd2/txd3 = MII tx data MII Transmit Enable (or SMII =ssync). The MAC asserts this signal when it drives valid data on the txd inputs. This signal must be synchronized to the tx_clk. MII Transmit Clock. Normally the STE101P drives tx_clk. 25 MHz for 100 Mbps operation. 2.5 MHz for 10 Mbps operation. Receive Error. The STE101P asserts this output when it receives invalid symbols from the network. This signal is synchronous to rx_clk. In Symbol (5B) Mode this pin functions as rxd4. Receive Data. The STE101P drives received data on these outputs, synchronous to rx_clk. rxd4 is driven only in Symbol (5B) Mode. *rxd0 = MII/RMII/SMII rx data *rxd1 = MII/RMII rx data *rxd2/rxd3 = MII rx data Receive Data Valid. MII RXDV (or RMII = CRSDV). The STE101P asserts This signal when it drives valid data on rxd. This output is synchronous to rx_clk. MII Receive Clock: This continuous clock provides reference for rxd, rx_dv, and rx_er signals. 25 MHz for 100 Mbps operation. 2.5 MHz for 10 Mbps operation. MII Collision Detection: The STE101P asserts this output when detecting a collision. This output remains High for the duration of the collision. This signal is asynchronous and inactive during full-duplex operation. MII Carrier Sense: During half-duplex operation (PR0:8=0), the STE101P asserts this output when either transmit or receive medium is non idle. During full duplex operation (PR0:8=1), crs is asserted only when the receive medium is non-idle. 52 tx_er I 52 58 57 56 55 txd4 txd3 txd2 txd1 txd0 I 54 tx_en I 53 tx_clk I/O 51 51 43 44 46 47 48 rx_er rxd4 rxd3 rxd2 rxd1 rxd0 rx_dv O O O 49 rx_clk O 59 col O 60 crs O 9/53 DataSheet 4 U .com www..com Pin description Table 1. Pin No. STE101P Pin description (continued) Name Type Description MII control interface Management Data Clock. Clock for the mdio serial data channel. One MDC transition is also required to complete a device reset. Maximum frequency is 2.5 MHz. Management Data Input/Output, Bi-directional serial data channel for PHY communication. Management Data Interrupt. When any bit in PR18 = 1, an active High output on this pin indicates status change in the corresponding bits in PR17. Interrupt is cleared by reading Register PR17 42 mdc I 41 mdio I/O 61 mdint OD Physical (twisted pair) interface 12 x1 I 25 MHz reference clock input. When an external 25 MHz crystal is used, this pin will be connected to one terminal of it. If an external 25 MHz clock source of oscillator is used, then this pin will be the input pin of it. 25 MHz reference clock output. When an external 25MHz crystal is used, this pin will be connected to another terminal of if. If an external clock source is used, then this pin should be left open. The differential Transmit outputs of 100Base-TX or 10Base-T, these pins directly output to the transformer. The differential Receive inputs of 100Base-TX or 10Base-T, these pins directly input from the transformer. Reference resistor/DC regulator output. Reference Resistor connecting pin for reference current, directly connect a 5K 1% resistor to Vss. LED display for 10Ms/s link status. This pin will be driven on continually when 10Mb/s network operating speed is detected. The pull-up/pull-down status of this pin is latched into the PR14 bit 7 during power up/reset. LED display for TX/RX Activity status. This pin will be driven on at a 10 Hz blinking frequency when either effective receiving or transmitting is detected. The status of this pin is latched into the PR14 bit 6 during power up/reset. I/O LED display for Link Status. This pin will be driven on continually when a good Link test is detected, and Blink during TX or RX activity if PR1B bit 9 = 0. The status of this pin is latched into the PR14 bit 5 during power up/reset. LED display for Full Duplex or Collision status. This pin will be driven on continually when a full duplex configuration is detected. This pin will be driven on at a 20 Hz blinking frequency when a collision status is detected in the half duplex configuration. The status of this pin is latched into the PR14 bit 4 during power up/reset. LED display for 100Ms/s link status. This pin will be driven on continually when 100Mb/s network operating speed is detected. The status of this pin is latched into the PR14 bit 3 during power up/reset. 11 21 23 19 18 15 x2 txp txn rxp rxn iref O O I O 38 ledr10 I/O 37 ledtr 36 ledl 35 ledc I/O 34 leds I/O 10/53 DataSheet 4 U .com www..com STE101P Table 1. Pin No. Pin description Pin description (continued) Name Type Description Configuration Control 0. When A/N is enabled, cfg0 determines operating mode advertisement capabilities in combination with cfg1 when mf0/ PR00:12 =1. (See Table 2) When A/N is disabled, cfg1 disables mlt3 and directly affects PR13:0 When cfg0 is Low, mlt3 encoder/decoder is enabled and PR13:1 =0. When cfg0 is High, mlt3 encoder/decoder is bypassed and PR13:1 = 1. Configuration Control 1. When A/N is enabled, cfg1 determines operating mode advertisement capabilities in combination with cfg1 when mf0/ PR00:12 =1. (See Table 2) When A/N is disabled, CFG1 enables Loopback mode and directly affects PR00 bit 14. When cfg1 is Low, Loopback mode is disabled and PR00:14 = 0. When cfg1 is High, Loopback mode is enabled and PR00:14 = 1. Reset (Active-Low). This input must be held low for a minimum of 1 ms to reset the STE101P. During Power-up, the STE101P will be reset regardless of the state of this pin. Reset will not be complete until >1ms plus an MDC transition. Reset In Progress. This output is used to indicate when the device has completed power-up/reset and the registers and functions can be accessed. When rip is High, power-up/reset has been successful and the device can be used normally When rip is Low, device reset is not complete. Auto MDI/MDIX disable NC for MII operation. Should be tied high for RMII/SMII operation. See Table 2. NC for MII operation. System clock for RMII (50MHz) and SMII (125MHz) Test pins. Should be tied to ground for normal operation Power Down. When High, forces STE101P into Power Down mode. This pin is OR'ed with the Power Down bit (PR00:11). During the Power Down mode, txp/txn outputs and all LED outputs are 3-stated, and the MII interface is isolated. Multi-function pins. Each mf pin internally drives different configuration functions. The functions of the five mf inputs are as shown in the table below. Pin mfo Function Auto negotiation Enable NRZ, NRZI conversion 4B/5B coding enable Scrambler operation disable 10/100Mbps speed select Reg. & Bit affected PR00:12 PR13:7 PR13:6 PR13:0 PR00:13 64 cfg0 I 63 cfg1 I 28 reset I 29 rip O 30 31 32 26, 33 mdix_dis cf2 sclk test, test_se 27 pwrdwn I 5 4 3 2 1 mf0 mf1 mf2 mf3 mf4 mf1 I mf2 mf3 mf4 The logic level of mf0-4 will determine the value that the affected bits will have upon reset of the STE101P. The operating functions of cfg0, cfg1, and fde change depending on the state of mf0 (Auto-Negotiation enabled or disabled). Table shows the relationship between cfg0, cfg1 and fde. 11/53 DataSheet 4 U .com www..com Pin description Table 1. Pin No. STE101P Pin description (continued) Name Type Description Full-duplex enable. When A/N is enabled, fde determines full-duplex advertisement capability in combination with cfg0 and cfg1. (See Table 2) When A/N is disabled, fde directly affects full-duplex operation and determines the value of PR00 bit 8 (Full/Half Duplex Mode Select). When fde is High, full-duplex is enabled and PR00:8 = 1. When fde is Low, full-duplex is disabled and PR00:8 = 0. nc (No Connection) - Should be left floating or pulled low for normal operation. 6 fde I 8, 22 nc Digital power pins 39 45, 62 25, 40, 50 ovdd dvdd gnd I I I IO ring power supply (3.3V) Digital power (3.3V) Ground Analog power pins 9, 13, 16, 17 7, 10, 14, 20, 24 vcca gnda 12/53 DataSheet 4 U .com www..com STE101P Hardware control interface 5 5.1 Hardware control interface Operating configurations The hardware control interface consists of the MF0, CFG <2:0> and FDE input pins. This interface is used to configure operating characteristics of the STE101P. The hardware control interface provides initial values for the MDIO registers, and then passes control to the MDIO Interface. Table 2 shows how to set up the desired operating configurations using the hardware control interface. Table 2. CFG decode Function MII mode / MLT3 enabled MII mode / MLT3 disabled MII mode/ local loopback disabled MII mode/ local loopback enabled MII mode / advertise 10HD MII mode / advertise 10HD /FD MII mode / advertise 100HD MII mode / advertise 100HD / FD MII mode / advertise 10/100 HD MII mode / advertise all SMII mode RMII mode MF0 0 0 0 0 1 1 1 1 1 1 x x FDE x x x x 0 1 0 1 0 1 x x CFG0 0 1 x x 0 0 1 1 1 1 0 0 CFG1 x x 0 1 1 1 0 0 1 1 0 1 CF2 0 0 0 0 0 0 0 0 0 0 1 1 Reg:Bit PR13:1 PR13:1 PR00:14 PR00:14 PR04:8,7,6,5 PR04:8,7,6,5 PR04:8,7,6,5 PR04:8,7,6,5 PR04:8,7,6,5 PR04:8,7,6,5 RS1C:12 RS1C:11 Note: When MF0 = 0, PR04 is configured to advertise all (i.e 8:5 = 4'b1111). When MF0=1, MLT3 is enabled and Loopback is disabled by default 5.2 LED / PHY address interface The LED output pins can be used to drive LED's directly, or can be used to provide status information to a network management device. The active state of each LED output driver is dependent on the logic level sampled by the corresponding PHY address input upon powerup/reset. For example, if a given PAD input is resistively pulled low then the corresponding LED output will be configured as an active high driver. Conversely, if a given PAD input is resistively pulled high then the corresponding LED output will be configured as an active low driver. These outputs are standard CMOS drivers and not open-drain. The STE101P PAD[4:0] inputs provide up to 32 unique PHY address options. An address selection of all zeros (00000) will result in a PHY isolation condition as a result of poweron/reset, as documented for Register PR00 bit 10. (See Section 7 for more detailed descriptions of device operation.) 13/53 DataSheet 4 U .com www..com Registers and descriptors description STE101P 6 Registers and descriptors description All of the management data control and status registers in the STE101P's register set are accessed via a Write or Read operation on the serial MDIO Port. This access requires a protocol described in the MII management Interface section. 6.1 Register list Table 3. Address 00h - 0d 01h - 1d 02h - 2d 03h - 3d 04h - 4d 05h - 5d 06h - 6d 07h - 7d 08h - 8d 10h - 16d 11h - 17d 12h - 18d 13h - 19d 14h - 20d 18h - 24d 19h - 25d 1ah - 26d 1bh - 27d 1ch - 28d 1dh - 29d 1eh - 30d 1fh - 31d 18h - 24d 1bh - 27d 1ch - 28d List of registers Reg. Index PR00 PR01 PR02 PR03 PR04 PR05 PR06 PR07 PR08 PR10 PR11 PR12 PR13 PR14 PR18 PR19 PR1A PR1B PR1C PR1D PR1E PR1F RS18 RS1B RS1C Name CNTRL STATS PHYID PHYID LDADV LPADV ANEGX LDNPG LPNPG XCNTL XCIIS XIE 100CTR XMC AUXCS AUXSS INRPT AUXM2 TSTAT AUXMD AMPHY BTEST XDCNT MISC AUX S3 Def.(1) Register description 0x0000 MII control register (Table 4) 0x7809 MII status register (Table 5) 0x0006 PHY identifier (HI) register (Table 6) 0x1c52 PHY identifier (LO) register (Table 7) 0x01e1 Auto negotiation advertisement register (Table 8) 0x0000 Auto negotiation link partner ability register (Table 9) 0x0004 Auto negotiation expansion register (Table 10) 0x2001 0x0000 Auto negotiation next page transmit register (Table 11) Auto negotiation link partner next page transmit register (Table 12) 0x0000 100BaseTX auxiliary control register (Table 13) 0x0000 Configuration information interrupt & status register (Table 14) 0x0000 Interrupt enable register (Table 15) 0x01c0 100BaseTX control register (Table 16) 0x0002 Mode control register (Table 17) 0x0030 Auxiliary control/status register (Table 18) 0x0000 Auxiliary status summary register (Table 19) 0x1f00 Interrupt register (Table 20) 0x000a Auxiliary mode 2 register (Table 21) 0x0820 Auxiliary error and general status register (Table 22) 0x0000 Auxiliary mode register (Table 23) 0x0000 Auxiliary PHY register (Table 24) 0x000b Shadow register enable (Table 25) 0x0000 100BaseTX disconnect counter register (Table 26) 0x0000 Misc/status/test/error register (Table 27) 0x0000 FIFO status (Table 28) 14/53 DataSheet 4 U .com www..com STE101P Table 3. Address 1dh - 29d 1eh - 30d Registers and descriptors description List of registers (continued) Reg. Index RS1D RS1E Name AUX M3 AUX S4 Def.(1) Register description 0x0004 FIFO control (Table 29) 0x0000 Packet/IPG length counter (Table 30) 1. Default value 6.2 Register description Table 4. Bit # 15 14 13 PR00 [0d00, 0x00]: MII control register Name Soft reset Local loop back Force 100 Auto negotiation enable Description 1 = Requires approx. 1 micro second to complete soft reset sequence 1 = Local Loop-back passes data from TX-> RX serial conversion analog logic 1= Forced 100Mb speed selection. Ignored if Auto Negotiation is enabled 1 = Software Auto Negotiation enable. Ignored if hardware pin strap enables Auto Negotiation 1= Channel is powered down. If this bit is set for all channels then the IO pad directions are forced and the device is in power down state. 1= Isolation mode. Related Pad outputs are forced to tri-state, inputs are ignored. 1= Restart Auto Negotiation. Auto Negotiation must be enabled for any effect. 1= Full Duplex. Only applies if auto negotiation is disabled 1= Collision test Reserved Reset value 0 0 P RW type R/W R/W R/W Type SC - 12 P R/W - 11 Power down 0 R/W - 10 Isolate 0 R/W - 9 Restart auto negotiation Full duplex Collision test --- 0 R/W SC 8 7 6~0 P 0 0 R/W R/W R/W - SC = Self clear (Clear following action), P=Pinstrap (Read at reset), R/W = Read/Write able 15/53 DataSheet 4 U .com www..com Registers and descriptors description STE101P Soft reset: In order to reset the STE101P by software control, a "1" must be written to the bit 15 of the Control Register using an MII write operation. The bit clears itself after the reset process is complete, and does not need to be cleared using a second MII write. Writes to other Control Register bits will have no effect until the reset process is completed, which requires approximately 1 microsecond. Writing a "0" to this bit has no effect. Since this bit is self-clearing, after a few cycles from a write operation, it will return a "0" when read. Local loopback: The STE101P may be placed into loop back mode by writing a "1" to bit 14 of the Control Register. The loop back mode may be cleared by writing a "0" to bit 14 of the Control Register, or by resetting the chip. When this bit is read, it will return a "1" when the chip is in software-controlled loop back mode, otherwise it will return a "0". Force 100: If Auto Negotiation is enabled, this bit has no effect on the speed selection. However, if Auto Negotiation is disabled by software control, the operating speed of the STE101P can be forced by writing the appropriate value to bit 13 of the Control Register. Writing a "1" to this bit forces 100BASETX operation, while writing a "0" forces 10BASE-T operation. When this bit is read, it returns the value of the software-controlled forced speed selection only. In order to read the overall state of forced speed selection, including both hardware and software control, use bit 8 of the Auxiliary Control Register. Auto negotiation enable: Auto negotiation can be disabled by one of two methods: hardware or software control. If the ANEN input pin is driven to a logic "0", auto negotiation is disabled by hardware control. If bit 12 of the Control Register is written with a value of "0", auto negotiation is disabled by software control. When auto negotiation is disabled in this manner, writing a "1" to the same bit of the Control Register or resetting the chip will reenable Auto Negotiation. Writing to this bit has no effect when Auto Negotiation has been disabled by hardware control. When read, this bit will return the value most recently written to this location, or "1" if it has not been written since the last chip reset. Power down: 1 = Channel is powered down. If this bit is set for all channels, then the IO pad directions are forced and the device is in power down state. Isolate: The PHY may be isolated from its Media Independent Interface by writing a "1" to bit 10 of the Control Register. All MII outputs will be tri-stated, except tx_clk, and all MII inputs will be ignored. Since the MII management interface is still active, the isolate mode may be cleared by writing a "0" to bit 10 of the Control Register, or by resetting the chip. When this bit is read, it will return a "1" when the chip is in isolate mode, otherwise it will return a "0". Restart auto negotiation: Bit 9 of the Control Register is a self-clearing bit that allows the Auto Negotiation process to be restarted, regardless of the current status of the Auto Negotiation state machine. In order for this bit to have an effect, Auto Negotiation must be enabled. Writing a "1" to this bit restarts the Auto Negotiation, while writing a "0" to this bit has no effect. Since the bit is self-clearing after only a few cycles, it always returns a "0" when read. The operation of this bit is identical to bit 9 of the Auxiliary PHY Register. Full duplex: By default, the STE101P powers up in half-duplex mode. The chip can be forced into full-duplex mode by writing a "1" to bit 8 of the Control Register while Auto Negotiation is disabled. Half-duplex mode can be resumed by writing a "0" to bit 8 of the Control Register, or by resetting the chip. Collision test: The COL pin may be tested during loop back by activating the collision test mode. While in this mode, asserting TXEN will cause the COL output to go high within 512 bit times. Deasserting TXEN will cause the COL output to go low within 4 bit times. Writing a "1"to bit 7 of the Control Register enables the collision test mode. Writing a "0" to this bit or resetting the chip disables the Collision Test mode. When this bit is read, it will return a "1" 16/53 DataSheet 4 U .com www..com STE101P Registers and descriptors description when the collision test mode has been enabled, otherwise it will return a "0". This bit should only be set while in loop back test mode. Reserved bits: All reserved MII register bits must be written as "0" at all times. Ignore the STE101P output when these bits are read. Table 5. Bit # 15 14 13 12 11 10~7 6 5 4 3 PR01 [0d01, 0x01]: MII status register Name Description Reset value 0 1 1 1 1 0 0 0 0 1 RW type RO RO RO RO RO RO R/W RO RO RO LH Type 100Base T4 ability Tied to 0. Not supported 100BaseTX FDX ability 100BaseTX ability 10BaseT FDX ability 10BaseT ability Reserved Preamble suppression Auto Negotiation complete Remote fault Auto negotiation ability Link status Tied to 1. Device is always 100BaseTX and Full Duplex capable Tied to 1. Device is always 100BaseTX Half Duplex capable. Tied to 1. Device is always 10BaseT and Full Duplex capable Tied to 1. Device is always 10BaseT Half Duplex capable --1= MII management frames can be accepted without the standard preamble 1 = Auto Negotiation Completed and registers 4,5,6 are now valid 1= Link Partner has signalled a far end fault condition Tied to 1. Device is always capable of Auto Negotiation 1=Link pass state established. 0=Link fail state "latched" after link pass state 1= Jabber condition detected. Transmission exceeded max number of bytes. 2 0 RO LL 1 Jabber detect 0 RO LH 0 Extended register Tied to 1. Device always supports the ability extended register set. 1 RO 100Base T4 ability: The STE101P is not capable of T4 operation, and will return a "0" when bit 15 of the status register is read. 100BaseTX FDX ability The STE101P is capable of 100BaseTX full-duplex operation, and will return a "1" when bit 14 of the status register is read. 100BaseTX ability: The STE101P is capable of 100BaseTX half-duplex operation, and will return a "1" when bit 13 of the status register is read. 10BaseT FDX ability: The STE101P is capable of 10BASE T full-duplex operation, and will return a "1" when bit 12 of the status register is read. 17/53 DataSheet 4 U .com www..com Registers and descriptors description STE101P 10BaseT ability: The STE101P is capable of 10BASE T half-duplex operation, and will return a "1" when bit 11 of the status register is read. Reserved bits: Ignore STE101P output when these bits are read. Preamble suppression: This bit is the only writable bit in the status register. Writing this bit to a "1" allows subsequent MII management frames to be accepted with or without the standard preamble pattern. When preamble suppression is enabled, only 2 preamble bits are required between successive Management Commands, instead of the normal 32. Auto negotiation complete: Bit 5 of the status register will return a "1" if the auto negotiation process has been completed, and the contents of registers 4, 5, and 6 are valid. Auto Negotiation ability: The STE101P is capable of performing IEEE Auto Negotiation, and will return a "1" when bit 4 of the status register is read, regardless of whether or not the Auto Negotiation function has been disabled Link status: The STE101P will return a "1" on bit 2 of the status register when the link state machine is in link pass, indicating that a valid link has been established. Otherwise, it will return a "0". When a link failure occurs after the link pass state has been entered, the link status bit will be latched at "0" and will remain so until the bit is read. After the bit is read, it becomes "1" if the link pass state has been entered again. Jabber detect: 10BASE-T operation only. The STE101P will return a "1" on bit 1 of the status register if a jabber condition has been detected. After the bit is read, of if the chip is reset, it reverts to "0". Extended register ability The STE101P supports extended capability registers, and will return a "1" when bit 0 of the Status Register is read. Several extended registers have been implemented in the STE101P, and their bit functions are defined later in this section. Table 6. Bit # PR02 [0d02, 0x02]: PHY Identifier (HI) register Name Description Part one of PHY Identifier. Assigned to the 3rd to 18th bits of the Organizationality Unique Identifier (OUI). 5the ST OUI is 0080E1 hex) Default value RW type 15~0 PHYID1 0006h R Table 7. Bit # PR03 [0d03, 0x03]: PHY Identifier (LO) register Name Description Part two of PHY Identifier. Assigned to the 19th to 24th bits of the Organizationality Unique Identifier (OUI). 5the ST OUI is 0080E1 hex) Model number of STE101P. Six-bit manufacture's model number Revision number of STE101P. Four-bit manufacture's revision number Default value RW type 15-10 PHYID2 000111b R 9-4 3-0 MODEL 000101b 0010b R R The STE101P Revision A for this register has a value of 0x1c51 18/53 DataSheet 4 U .com www..com STE101P Registers and descriptors description The STE101P Revision B for this register has a value of 0x1c52. This allows identification of the revision of the device via software reading of this register. Table 8. Bit # 15 14 13 12,11 10 9 8 7 6 5 4~0 PR04 [0d04, 0x04]: Auto negotiation advertisement register Name Nxt page Reserved Remote fault Reserved Pause 100Base T4 advertise 100BaseTX FDX advertise 100BaseTX advertise 10BaseT FDX advertise 10BaseT advertise Advertised selector field[4:0] Description 1= Supports next page function --Remote fault indicator to be sent to the link partner during auto negotiation --1 = Supports PAUSE operation of flow control for full duplex link Advertise T4. Not supported Advertise 100MB Full duplex Advertise 100MB Advertise 10MB Full duplex Advertise 10MB Advertise 802.3 class of PHY transceivers. Reset value 0 0 0 0 1 0 1 1 1 1 00001 [4:0] R/W R/W R/W R/W R/W R/W R/W R/W RW type R/W Type - Nxt Page: The STE101P supports next page capability. Reserved: Ignore output when read Remote fault: Writing a "1" to bit 13 of the Advertisement register causes a Remote Fault indicator to be sent to the Link Partner during Auto Negotiation. Writing a "0" to this bit or resetting the chip clears the Remote Fault transmission bit. This bit returns the value last written to it, or else "0" if no write has been completed since the last chip reset. Pause: The use of this bit is independent of the negotiated data rate, medium, or link technology. The setting of this bit indicates the availability of additional DTE capability when full-duplex operation is in use. This bit is used by one MAC to communicate Pause Capability to its Link Partner, and has no effect on PHY operation. Advertisement bits: Bits 9:5 of the Advertisement register allow the user to customize the ability information transmitted to the Link Partner. The default value for each bit reflects the abilities of the STE101P. By writing a "1" to any of the bits, the corresponding ability will be transmitted to the Link Partner. Writing a "0" to any bit causes the corresponding ability to be suppressed from transmission. Resetting the chip restores the default bit values. Reading the register returns the values last written to the corresponding bits, or else the default values if no write has been completed since the last chip reset. Even though that bit 9, Advertise 100BASE-T4 is writable, it should never be set since the STE101P is incapable of the T4 operation. 19/53 DataSheet 4 U .com www..com Registers and descriptors description STE101P Advertised selector: Bits 4:0 of the Advertisement register contain the fixed value "00001", indicating that the chip belongs to the 802.3 class of PHY transceivers. Table 9. Bit # 15 14 13 12,11 10 9 8 7 6 5 4~0 PR05 [0d05, 0x05]: Auto negotiation link partner ability register Name LP nxt page LP ack LP remote fault Reserved LP pause LP 100Base T4 LP 100BaseTX FDX LP 100BaseTX LP 10BaseT FDX LP 10BaseT LP selector field[4:0] Description 1= Link Partner supports next Page function 1= Successful Reception of Link Partner's link control word 1 = Link Partner is signalling a remote fault ---Used by MAC in full duplex to allow additional DTE ability Link Partner 100Base T4 ability Link Partner 100MB Full duplex ability Link Partner 100MB ability Link Partner 10MB Full duplex ability Link Partner 10MB ability Link partner class of PHY transceivers Reset value 0 0 0 0 0 0 0 0 0 0 0 RW type RO RO RO RO RO RO RO RO RO RO RO Type - LP nxt page: Bit 15 of the link partner ability register returns a value of "1" when the Link Partner implements the Next Page function and has Next Page information that it wants to transmit. LP ack: Bit 14 of the link partner ability register is used by Auto Negotiation to indicate that a device has successfully received its Link Partner's Link Code Word. LP remote fault: Bit 13 of the link partner ability register returns a value of "1" when the Link Partner signals that a remote fault has occurred. The STE101P simply copies the value to this register and does not act upon it. Reserved: ignore when read. LP pause: Indicates that the link partner pause bit is set. LP selector field: Bits 4:0 of the link partner ability register reflect the value of the Link Partner's selector field. These bits are cleared any time Auto Negotiation is restarted or the chip is reset. Advertisement bits: Bits 9: 5 of the link partner ability register reflect the abilities of the Link Partner. A "1" on any of these bits indicates that the Link Partner is capable of performing the corresponding mode of operation. Bits 9:5 are cleared any time Auto Negotiation is restarted or the STE101P is reset. 20/53 DataSheet 4 U .com www..com STE101P Table 10. Bit # 15~5 4 3 2 1 0 --Parallel detection fault Registers and descriptors description PR06 [0d06, 0x06]: Auto negotiation expansion register Name Reserved Parallel detection fault detected by the Auto Negotiation FSM Description Reset value 0 0 0 1 0 0 RW type RO RO RO RO RO RO Type - LP next page able 1= Link Partner is Next Page capable LD next page able Page received LP auto negotiation able Tied to 1. Device is always next page capable 1= New link control work received from the link partner 1 = Link Partner has Auto Negotiation capability Reserved: Ignore when read. Parallel detection fault: Bit 4 of the Auto Negotiation Expansion Register is a read-only bit that gets latched high when a parallel detection fault occurs in the Auto Negotiation state machine. For further details, please consult the IEEE standard. The bit is reset to "0" after the register is read, or when the chip is reset. LP next page able: Bit 3 of the Auto Negotiation Expansion Register returns a "1" when the Link Partner has Next Page capabilities. It has the same value as bit 15 of the Link Partner Ability Register. Page received: Bit 1 of the Auto Negotiation Expansion Register is latched high when a new Link Code Word is received from the Link Partner, checked, and acknowledged. It remains high until the register is read, or until the chip is reset. LP auto negotiation able: Bit 0 of the Auto Negotiation Expansion Register returns a "1" when the Link Partner is known to have Auto Negotiation capability. Before any Auto Negotiation information is exchanged, or if the Link Partner does not comply with IEEE Auto Negotiation, the bit returns a value of "0". Table 11. Bit # PR07 (0d07, 0x07): Auto negotiation next page transmit register Name Description Identifies this as the last page to be transmitted 1 = Additional Next Page(s) will follow. Acknowledge 0 = Unformatted Page. 1 = Message page. 1 = Device can comply with message Arbitration control used to manage next page exchange. Reset value RW type Type 15 14 13 12 11 Next page Ack Msg page Ack2 Toggle 0 0 1 0 0 000000 0001 R/W R/W R/W R/W RO - 10~0 Message/ Unformatted code Code Field field R/W - 21/53 DataSheet 4 U .com www..com Registers and descriptors description Next page: Indicates whether this is the last Next Page to be transmitted. Msg page: Differentiates a Message Page from an Unformatted Page. Ack2: Indicates that a device has the ability to comply with the message. STE101P Toggle: Used by the Arbitration function to ensure synchronization with the Link Partner during Next Page exchange. Message code field: An eleven-bit wide field, encoding 2048 possible messages. Unformatted code field: An eleven-bit wide field, which may contain an arbitrary value. Table 12. Bit # PR08 [0d08, 0x08]: Auto negotiation link partner next page transmit reg. Name Descriptions Identifies this as the last page to be transmitted 1 = Additional Next Page(s) will follow. Acknowledge 0 = Unformatted Page. 1 = Message page. 1 = Device can comply with message Arbitration control used to manage next page exchange. Reset Val RW Type Type 15 14 13 12 11 Next page Ack Msg page Ack2 Toggle 0 0 0 0 0 RO RO RO RO RO - 10~0 Message/ Code Field Unformatted code field 0 RO - Next page: Indicates whether this is the last Next Page. Msg page: Differentiates a Message Page from an Unformatted Page. Ack2: Indicates that Link Partner has the ability to comply with the message. Toggle: Used by the Arbitration function to ensure synchronization with the Link Partner during Next Page exchange. Message code field: An eleven-bit wide field, encoding 2048 possible messages. Unformatted code field: An eleven-bit wide field, which may contain an arbitrary value. Table 13. Bit # 15~8 7 6 5 4~3 PR10 [0d16, 0x10]: 100BaseTX auxiliary control register Name Reserved Bypass symbol Reserved FEF enable Reserved --1= Bypass the Symbol alignment. Used in conjunction with bit[10] to place 5B codes directly onto MII and RXER pins --1 = Enable Far-End fault detection --Descriptions Reset Val 0 0 0 0 0 RW Type R/W R/W R/W R/W R/W Type - 22/53 DataSheet 4 U .com www..com STE101P Table 13. Bit # Registers and descriptors description PR10 [0d16, 0x10]: 100BaseTX auxiliary control register Name Descriptions 1 = Enable Extended FIFO feature. FIFO fills and empties according to LP speed. 1 = Enable RMII Out of Band signalling --Reset Val 0 0 0 RW Type R/W R/W R/W Type 2 1 0 Extended FIFO RMII_OOBS Reserved - Reserved: Write as "0", Ignore when read. Bypass symbol: Receive symbol alignment may be bypassed by writing a "1" to bit 7 of MII Register 10h. When used in conjunction with the bypass 4B/5B encoder/decoder bit, unaligned 5B codes will be placed directly on the RXER and RXD [3:0] pins. Reserved: The Reserved bits of the 100BaseTX Auxiliary Control Register must be written as "0" at all times. Ignore the STE101P outputs when these bits are read. Table 14. Bit # 15~12 11 10 9 8 7 6 5 4 3 2 1 0 PR11 [0d17, 0x11]: 100BaseTX Auxiliary Status Register Name Reserved FIFO over run Reserved Speed Duplex Pause function --1=FIFO over run occurred. PHY speeds or packet length may be too extreme --1=100Mbps 0=10Mbps 1=Full Duplex 0=Half Duplex 1=Pause Function Enabled 0= Pause Function Disabled Description Reset value 0 0 0 P P 0 0 0 0 0 0 0 0 RW type R/W RO RO RO RO RO RO RO RO RO RO RO RO Type LH LH LH LH LH LH LH Auto neg interrupt 1=Interrupt if Auto Neg completed Remote fault interrupt Link down interrupt Link code word recd interrupt Parallel detection fault Auto neg page recd. Ref interrupt 1= Interrupt if Remote Fault detected 1=Interrupt if Link down (following link up condition) 0=No Link Code Word detected 1=Interrupt if Link Code Word received 1= Interrupt if Parallel Detection fault 1=Interrupt if Auto negotiation page received 1=Interrupt if 64K errant packets received LH = Latched High (Clear after read), LL = Latched Low (Clear after read) 23/53 DataSheet 4 U .com www..com Registers and descriptors description Table 15. Bit # 15~7 6 5 4 3 2 1 0 STE101P PR12 [0d18, 0x12]: Interrupt enable register Name Reserved Auto Neg Complete Int Enable RF Int Enable LD Int Enable Auto Neg Ack Int Enable Par Det Int Enable Auto Neg Page Recd Int enable --1=Enable Auto Negotiation completed Interrupt 1=Enable Remote Fault Interrupt 1=Enable Link Down Interrupt 1=Enable Auto Negotiation Acknowledge Interrupt 1=Enable Parallel Detection Fault Interrupt 1=Enable Auto negotiation Page Received Interrupt Description Reset value 0 0 0 0 0 0 0 0 RW type RO R/W R/W R/W R/W R/W R/W R/W Type _ _ _ - RX Error Buffer Int 1=Enable RX error Buffer full Interrupt Enable Table 16. Bit # 15~14 13 12 11 10 9 8 7 6 5 PR13 [0d19, 0x13]: 100BaseTX control register Name Reserved Disable RX err counter Auto Neg Complete RX Voltage peakpeak Reserved --1=Disable receive error counter 1=Auto Negotiation process completed 1=Receive voltage peak-to-peak 1.4VPP --Descriptions Reset Val 0 0 0 0 0 0 1 P P 0 RW Type RO R/W RO R/W R/W R/W R/W R/W R/W R/W Type - Enable Loop back 1=Enable remote loop back Enable DC rest 1=Enable DC restoration (Baseline (Baseline wander) wander) Enable NRZI to NRZ Enable 4B/5B Transmit Isolation 1=Enable NRZI to NRZ data conversion 1=Enable 4B/5B encoder and decoder 1=Transmit Isolation (Isolate MII and TX +/-). PHY address = <00000> at reset 24/53 DataSheet 4 U .com www..com STE101P Table 16. Bit # Registers and descriptors description PR13 [0d19, 0x13]: 100BaseTX control register (continued) Name Descriptions 000: In auto negotiation 001: 10Base-T Half Duplex 010: 100Base-TX Half Duplex 011: Reserved 100: Reserved 101: 10Base-T Full Duplex 110: 100Base-TX Full Duplex 111: Isolation, Auto Neg Disable 1=MLT3 Disabled 1=Scrambler and descrambler logic is disabled Reset Val RW Type Type 4~2 CMode 0 RO - 1 0 MLT3 Disable Scrambler/descra mbler disable P P R/W R/W - Table 17. Bit # 15~12 11 10~8 7~3 2 1 0 PR14 [0d20, 0x14]: XCVR Mode control register Name Reserved Link Detect Reserved PHY address Reserved Preamble suppression Reserved --1=Reduces 10Base-T squelch level to increase cable length --Phy Address[4:0] value of <00000> latched during reset = isolation mode --1=Accept management MDIO frames with the Preamble suppressed --Descriptions Reset Val 0 0 0 P 0 1 0 RW Type RO R/W RO R/W RO R/W RO Type - Table 18. Bit # PR18 [0d24, 0x18]: Auxiliary control register Name Description 1= Disable Jabber detection, which will shut off the transmit when the packet length exceeds IEEE defined length 1= Disable link integrity FSM checking and force the device to link pass state --Increase HSQ or decrease LSQ squelch levels of incoming 10 BaseT packets Program DAC output (Not supported) Reset value 0 RW type R/W Type 15 Jabber disable 14 13~8 7 6 5 4 3 Force link Reserved HSQ LSQ Edge rate[1] Edge rate[0] Auto Negotiation enable 0 0 0 1 R/W RO R/W R/W 1 = Auto negotiation enabled P RO 25/53 DataSheet 4 U .com www..com Registers and descriptors description Table 18. Bit # 2 1 0 STE101P PR18 [0d24, 0x18]: Auxiliary control register (continued) Name Force 100 Speed 100 indicate FDX indicate Description 1 =Speed forced to 100MB 1 = Speed is 100MB 1 = Full duplex mode selected Reset value P 0 P RW type RO RO RO Type P = Pin Strap (Read at reset) Jabber disable: 10BASE-T operation only. Bit 15 of the Auxiliary Control Register allows the user to disable the Jabber Detect function, defined in the IEEE standard. This function shuts off the transmitter when a transmission request has exceeded a maximum time limit. By writing a "1" to bit 15 of the Auxiliary Control Register, the Jabber Detect function is disabled. Writing a "0" to this bit or resetting the chip restores normal operation. Reading this bit returns the value of Jabber Detect Disable. Force link: Writing a "1" to bit 14 of the Auxiliary Control Register allows the user to disable the Link integrity state machines, and place the STE101P into forced Link Pass status. Writing a "0" to this bit or resetting the chip restores the Link Integrity functions. Reading this bit returns the value of Link Integrity Disable. HSQ and LSQ: Extend or decrease the squelch levels for detection of incoming 10BASE-T data packets. The default squelch levels implemented are those defined in the IEEE standard. The high and low squelch levels are useful for situations where the IEEEprescribed levels are inadequate. The squelch levels are used by the CRS/LINK block to filter out noise and recognize only valid packet preambles and link integrity pulses. Extending the squelch levels allows the STE101P to operate properly over long range cable lengths. Decreasing the squelch levels may be useful in situations where there is a high level of noise present on the cables. Reading these two bits returns the value of the squelch levels. Edge rate: Control bits used to program the transmit DAC output edge rate in 100BASE-TX mode. These bits are logically AND'ed with the ER[1:0] input pins to produce the internal edge-rate controls (Edge_Rate[1] AND ER[1], Edge_Rate[0] AND ER[0]). Auto negotiation enable: A read-only bit that indicates whether Auto Negotiation has been enabled or disabled on the STE101P. A combination of a "1" in bit 12 of the control register and a logic "1" on the ANEN input pin is required to enable Auto Negotiation. When Auto Negotiation is disabled, bit 3 of the Auxiliary Control Register returns a "0". At all other times, it returns a "1". Force 100: A read-only bit that returns a value of `0" when one of the following two cases is true: 1. 2. The ANEN pin is low AND the F100 pin is low. Bit 12 of the control register has been written "0" AND bit 13 of the control register has been written "0". When bit 8 of the Auxiliary Control Register is "0", the speed of the chip will be 10BASE-T. In all other cases, either the speed is not forced (Auto Negotiation is enabled), or the speed is forced to 100BaseTX. Speed 100 indicate: Bit 1 of the Auxiliary Control Register is a read-only bit that shows the true current operation speed of the STE101P. A "1" bit indicates 100BaseTX operation, while a "0" indicates 10BASE-T. Note that while the Auto Negotiation exchange is performed, the STE101P is always operating at 10BASE-T speed. 26/53 DataSheet 4 U .com www..com STE101P Registers and descriptors description FDX Indicate: Bit 0 of the Auxiliary Control Register is a read-only bit that returns a "1" when the STE101P is in full-duplex mode. In all other modes, it returns a "0". Table 19. Bit # 15 14 13 12 11 PR19 [0d25, 0x19]: Auxiliary status register Name Auto negotiation complete Auto negotiation ack Auto negotiation detect LP auto negotiation ability Auto negotiation pause Description 1 = Auto Negotiation completed 1= Auto Negotiation completed acknowledge state 1= Auto Negotiation entered acknowledge state 1 = Auto Negotiation Link Partner ability detect 1=LD and LP pause bits set during Auto Negotiation Highest Common Denominator determined by Auto Negotiation: 000= NO common denominator 001=10BaseT 010=10BaseT / Full Duplex 011=100BaseTX 100=100BaseT4 (Not Supported) 101=100BaseTX / Full Duplex 11x=Not defined 1=Parallel detection fault detected Reset value 0 0 0 0 0 RW type RO RO RO RO RO Type LH LH LH - 10~8 Auto negotiation HCD 0 RO 7 6 5 4 3 2 1 0 Parallel detection fault 0 0 0 0 0 0 0 0 RO RO RO RO RO RO RO RO LH LH LH LH LL LH LP remote far end 1=Link Partner signalled far-end fault fault condition LP page received 1=New page received from LP LP Auto 1=Link Partner is capable of Auto Negotiation ability Negotiation SP100 indicate Link status Auto negotiation enable Jabber detect 1=100 Mbps 1=Link pass state 1=Auto Negotiation enabled 1=Jabber condition detected LH = Latched High (Clear after reset) 27/53 DataSheet 4 U .com www..com Registers and descriptors description Table 20. Bit # STE101P PR1A[0d26, 0x1A]: Interrupt register Name Description Full duplex LED Enable. Affects which status signals are sent out on the serial LED data. Interrupt enable. effects which status signals are sent out on the serial LED data. Note: bits [15:14} are mutually exclusive --1= Changes in full-duplex will not generate an interrupt 1 = Speed will not generate an interrupt 1 = Changes in link status will not generate an interrupt 1= None of the interrupts above will generate an Interrupt. Master enable --1=Any interrupt was detected 1 = Half / Full duplex change 1= 10/100 Speed change 1 = Link status change Status of the INTR# pin Reset value 0 RW type R/W Type 15 FDX enable - 14 Interrupt enable 0 R/W - 13~12 11 10 9 8 7~5 4 3 2 1 0 Reserved FDX Mask SPD Mask Link Mask INTR Mask Reserved Global Interrupt FDX Interrupt Speed Interrupt Link Interrupt Interrupt status 0 1 1 1 1 0 0 0 0 0 0 R/W R/W R/W R/W R/W RO RO RO RO RO RO LH LH LH LH LH = Latched High (Clear after reset) FDX enable: Setting this bit enables the FDX LED mode. Bits 14 and 15 of this register are mutually exclusive. Only one may be set at a time. When FDXLED mode is enabled, XMTLED# becomes FDXLED# and RCVLED# becomes ACTLED#. INTR enable: Setting this bit enables Interrupt Mode. Bits 14 and 15 of this register are mutually exclusive. Only one may be set at a time. When Interrupt Mode is enabled, XMTLED# becomes INTR# and RCVLED# becomes ACTLED#. Side Note: if both bits 14 and 15 are set at the same time, the FDXLED# will override the INTR# output, even though the interrupt's FDX, SPD, and LINK change status bits will behave as in normal interrupt operation. FDX mask: When this bit is set, changes in Duplex mode will not generate an interrupt. SPD mask: When this bit is set, changes in operating speed will not generate an interrupt. LINK mask: When this bit is set, changes in Link Status will not generate an interrupt. INTR mask: Master Interrupt Mask. When this bit is set, no interrupts will be generated, regardless of the state of the other MASK bits. FDX interrupt: A "1" indicates a change of the Duplex status since last register read. Register read clears the bit. 28/53 DataSheet 4 U .com www..com STE101P Registers and descriptors description Speed interrupt: A "1" indicates a change of the Speed status since last register read. Register read clears the bit. Link interrupt: A "1" indicates a change of the Link status since last register read. Register read clears the bit. Interrupt status: Represents status of the INTR# pin. A "1" indicates that the interrupt mask is off and that one or more of the change bits are set. Register read clears the bit. Table 21. Bit # 15~10 11~10 9 8 7 6 5 4 PR1B [0d27, 0x1B]: Auxiliary mode 2 register Name Reserved Reserved LED no flash Reserved Block 10Base-T echo Traffic meter LED Activity LED force Serial LED enable 1=Block 10Base-T echo data 1=Traffic Meter LED Mode On 0=Traffic Meter LED Mode Off 1=Activity LEDs forced on 0=Activity LEDs not forced 1=Serial LED Mode enabled 0=Serial LED Mode disabled 1=SQE not transmitted in 10Base-T half-duplex 0=SQE transmitted in 10Base-T halfduplex Not supported Not supported ------1= Link LED will not blink for Tx/Rx 0= Link LED blinks with Tx/Rx activity Description Reset value 0 0 0 0 1 1 0 0 RW type RO R/W R/W RO R/W R/W R/W R/W Type - 3 SQE disable 1 R/W - 2 1 0 Activity LED enable Qualified parallel detect Reserved 0 1 0 R/W R/W RO - LED no flash: Default 0. When set = 1, this bit will cause the Link LED (ledl, pin 36) to not blink when there is Tx/Rx activity, but be driven on continually when a good link is detected. In the default state (LED_No_Flash=0), the Link LED will be driven on when a good link is detected, and momentarily blink off and on at a 10Hz rate during Tx/RX activity. Block 10BaseT echo: Default 0. When enabled during 10BASE-T half-duplex transmit operation, the TXEN signal will not echo onto the RXDV pin. The TXEN will echo onto the CRS pin, and the CRS deassertion directly follows the TXEN deassertion Traffic meter LED: Default 0. When asserted, the Receive and Transmit (Activity) LED's (XMTLED# and RCVLED# pins) will not blink based on the internal LED-CLK (approximately 80ms ON time). Instead, they will blink based on the rate of Receive and Transmit activity. Each time a Receive or Transmit operation occurs, the respective LED will 29/53 DataSheet 4 U .com www..com Registers and descriptors description STE101P turn on for a minimum of 5ms. With light traffic, the LED's will blink at a low rate. During medium to heavy traffic (packets within 5ms of each other), the LED's will remain on. Activity LED force: Default 0. When asserted, the Receive and Transmit (Activity) LED's (XMTLED# and RCVLED# pins) will be turned on. When 0, will have no affect on the Activity LED's. The Activity Force ON bit has a higher priority than Activity LED Force Inactive, bit 4, Register 1Dh. Serial LED enable: Default 0. When asserted, the 4 slices' LED outputs will be serially shifted out on the 2nd slices' LED outputs. The sequence of outputs for the different Serial modes are: FDX, `1', Speed, Link, FDX, Activity when the FDXLED mode is set and, FDX, `1', Speed, Link, Transmit, Receive, when neither interrupt nor FDXLED modes are selected. When this bit is 0, the four LED outputs per slice will be operated in parallel. SQE disable: Default 0. When asserted, will disable SQE pulses when operating in 10BASE-T half-duplex mode Qualified parallel detect: This bit allows the Auto Negotiation /Parallel Detection process to be qualified with information in the Advertisement register. Default value is 0. Table 22. Bit # 15~14 13 12 11 10 9 8~4 3 2 1 0 PR1C[0d28, 0x1C]: 10Base-T error and general status register Name Reserved MDIX status MDIX swap MDIX disable Manchester code error EOF error Reserved Auto negotiation enable Force 100 SP100 FDX indicate --1=MDIX is used 0=MDI configuration is used 1=Force MDIX 0=MDI or MDIX if MDIX is enabled 1=Disable MDIX 0=Autodetect and set MDI or MDIX Not supported 1=End of Frame detection error (Jabber detection - 10BaseT) --1=Auto Negotiation enable 1=100Mbs mode forced 1=100Mbps speed selected 1=Full duplex mode selected Description Reset value 0 0 0 P 0 0 0 P P 0 0 RW type RO RO R/W R/W RO RO RO RO RO RO RO Type - P=Pin strap (Read at reset) MDIX status: This bit indicates whether MDI or MDIX is in use. MDIX swap: Setting this bit forces the device to MDIX. When this bit is 0, the MDIX status will be determined by Auto-Negotiation if Auto-MDIX is enabled. MDIX disable: Setting this bit disables Auto detection and negotiation of MDIX. Clearing this bit enables Auto MDIX 30/53 DataSheet 4 U .com www..com STE101P Registers and descriptors description Manchester code error: Indicates that a Manchester code violation was received. This bit is only valid during 10BASE-T operation. EOF error: Indicates the EOF (end of frame) sequence was improperly received, or not received at all. This error bit is only valid during 10BASE-T operation. Auto negotiation enable: A read-only bit that indicates whether Auto Negotiation has been enabled or disabled on the STE101P. A combination of a "1" in bit 12 of the Control register and a logic "1" on the ANEN input pin is required to enable Auto Negotiation. Force 100: A read-only bit that returns a value of "0" when one of the following two cases is true: 1. 2. The ANEN pin is low AND the F100 pin is low. Bit 12 of the Control register has been written "0" AND bit 13 of Control Register has been written "0". When bit 8 of the Auxiliary Control Register is "0", the speed of the chip will be 10BASE-T. In all other cases, either the speed is not forced (Auto Negotiation is enabled), or speed is forced to 100 BASE-X. SP 100: A read-only bit that shows the true current operation speed of the STE101P. A "1" bit indicates 100BaseTX operation, while a "0" indicates 10BASE-T. Note that while the Auto Negotiation exchange is performed, the STE101P is always operating at 10BASE-T speed. FDX indicate: A read-only bit that returns a "1" when the STE101P is in full-duplex mode. In all other modes, it returns a "0". Table 23. Bit # 15~5 4 3 2 1 0 PR1D[0d29, 0x1D]: control register Name Reserved Description --Reset value 0 0 0 0 0 0 RW type RO R/W R/W R/W R/W R/W Type - Force activity LED 1=Disables the Activity LED output pin Force Link LED Reserved Block TXEN Reserved 1=Disables the Link LED output pin --1=Short IPG's <(4) TXC cycles will insert (2) IDLE cycles prior to next packet --- Reserved: Write as "000h", ignore when Read. Force activity LED: When set to "1", the XMTLED# and RCVLED# output pins are forced into their inactive state, regardless of the mode (normal, FDX, Interrupt, or Serial) these outputs are configured to. When "0", XMTLED# and RCVLED# output pins are enabled. Force link LED: When set to "1", the Link LED output pin if forced into its inactive state. When "0", Link LED output is enabled. Block TXEN: When this mode is enabled, short IPG's of 1, 2, 3, or 4 TXC cycles will all result in the insertion of two IDLE's before the beginning of the next packet's JK symbols. 31/53 DataSheet 4 U .com www..com Registers and descriptors description Table 24. Bit # STE101P PR1E[0d30, 0x1E]: Auxiliary PHY register Name Description Reset value 0 0 0 RW type RO RO RO Type 15 14 13 HCD 100Base-TX 1=Auto Negotiation selected 100BaseTX full-duplex FDX HCD 100Base-T4 HCD 100Base-TX HCD 10Base-T FDX 1=Auto Negotiation selected 100 BaseT4 (Not supported) 1=Auto Negotiation selected to 100BaseTX 1=Auto Negotiation selected to 10BaseT full-duplex 1=Auto Negotiation selected to 10BaseT --1=Restart Auto Negotiation. Auto Negotiation must be enabled for any effect 1=Auto Negotiation process Completed --1=Auto Negotiation Acknowledge completed 1=Auto Negotiation waiting for LP Ability 1=Super Isolate Mode 0=Normal Operation ----Reserved - 12 0 RO - 11 10~9 8 HCD 10Base-T Reserved Restart Auto negotiation Auto negotiation complete Reserved Auto negotiation ack Auto negotiation ability Super isolate Reserved Reserved RXER code 0 0 0 RO RO R/W SC 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 RO RO RO RO R/W RO R/W R/W - SC= Self Clear (Clear following action) HCD 10BaseT: Bits 15: 11 of the Auxiliary PHY Register are five read-only bits that report the Highest Common Denominator (HCD) result of the Auto Negotiation process. Immediately upon entering the Link Pass state after each reset or Restart Auto Negotiation, only one of these five bits will be a "1". The Link Pass state is identified by a "1" in bit 6 or 7 of this register. The HCD bits are reset to "0" every time Auto Negotiation is restarted or the STE101P is reset. Note that for their intended application, these bits will uniquely identify the HCD only after the first Link Pass after reset or restart of Auto Negotiation. On later Link Fault and subsequent re-negotiations, if the ability of the Link Partner is different, more than one of the above bits may be active. These bits are only set for full Auto Negotiation handshake, and not for Parallel Detection of Forced speed modes. Note that bit 14, HCD_T4, will never be set in the STE101P. Reserved: Ignore when read 32/53 DataSheet 4 U .com www..com STE101P Registers and descriptors description Restart auto negotiation: A self-clearing bit that allows the Auto Negotiation process to be restarted, regardless of the current status of the state machine. For this bit to work, Auto Negotiation must be enabled. Writing a "1" to this bit restarts Auto Negotiation. Since the bit is self-clearing, it always returns a "0" when read. The operation of this bit is identical to bit 9 of the Control Register. Auto negotiation complete: This read-only bit returns a "1" after the Auto Negotiation process has been completed. It remains "1" until the Auto Negotiation is restarted, a Link Fault, occurs, or the chip is reset. If Auto Negotiation is disabled, or the process is still in progress, the bit returns a "0". Auto negotiation ack: This read-only bit is set to "1" when the Arbitrator state machine exits the Acknowledged Detect state. It remains high until the Auto Negotiation process is restarted, or the STE101P is reset. Auto negotiation ability: This read-only bit returns a "1" when the Auto Negotiation state machine is in the Ability Detect state. It enters this state a specified time period after the Auto Negotiation process begins, and exits after the first FLP burst or link pulses are detected from the Link Partner. This bit returns a "0" any time the Auto Negotiation state machine is not in the Ability Detect state. Super isolate: Writing a "1" to this bit places the STE101P into the Super Isolate mode. Similar to the Isolate mode, all MII inputs are ignored, and all MII outputs are tri-stated. Additionally, all link pulses are suppressed. This allows the STE101P to coexist with another PHY on the same adapter card, with only one being activated at any time. RXER code: Writing a "1" to bit 0 of the Auxiliary Mode Register enables the RXER Code mode during 10BASE-T operation. In this mode, when a receive data error occurs, indicated by pins RXDV=1 and RXER=1, the RXD[3:0] bus will contain a non-zero 4-bit encoded value indicating the type of error. This feature provides the user with more detailed information regarding the status of the system. Writing a "0" to this bit or resetting the chip restores normal operation. Note that this mode does not disrupt normal communication with the MAC layer, and can safely be used at all times. Also, note that the RXER Code mode is not available in 10BASE-T Serial mode. In 100BaseTX operation, the RXER code mode is always active. Table 25. Bit # 15~8 7 6~0 PR1F[0d31, 0x1F]: Shadow register enable Name Reserved Shadow enable Reserved --1= Enable Shadow registers --0 Description Reset value RW type RO R/W RO Type Table 26. Bit # 15 14 13~0 RS18 [0d24, 0x18]: 100BaseTX Disconnect Counter Register Name LP fast LP slow Reserved Description 1=Link Partner recovered clock is faster than the local reference clock 1=Link Partner recovered clock is slower than the local reference clock --Reset value 0 0 0 RW type RO RO R/W Type - 33/53 DataSheet 4 U .com www..com Registers and descriptors description Table 27. Bit # 15 STE101P RS1B [0d27, 0x1B]: MISC Status/error/test register Name MLT3 detect Description 1= MLT3 signalling is enabled with no errors detected Cable length (meters) decode as follows: 000 <= 20 001 = 20-40 010 = 40-60 011 = 60-80 100 =80-100 101 =100-120 110 = 120-140 111 = >140 --LED Test controls. Speed up clock for simulation Reset value 0 RW type RO Type - 14~12 TX cable length 0 RO - 11 10 9 8 7 6 5 4 3 2~0 Reserved LED test cntrl 0 0 0 0 0 0 0 0 0 0 RO R/W RO RO RO RO RO RO RO R/W LH LH LH LH LH LH - Descrambler 1=Descrambler is locked on RX stream Locked False carrier 1=False carrier detected detect Bad ESD detect 1=Bad ESD detected RXER detect 1=RX(100) error detected TXER detect 1=TX(100) error detected Lock error detect MLT3 error detected Reserved 1=Lock error detected 1=MLT3 error detected --- 34/53 DataSheet 4 U .com www..com STE101P Table 28. Bit # 15~13 12 11 10 9~8 7 6 5 4 3~0 Registers and descriptors description RS1C[0d28, 0x1C]: Auxiliary status 3 - FIFO status register Name Reserved SMII mode RMII mode MII mode Reserved FLP detect NLP detect Link Break Link Fail --1 = SMII mode 1 = RMII mode 1 = MII mode --1=Fast Link Pulse detection 1=Normal Link Pulse detection 1=Link Break timer expired 1=Link fail timer expired Description Reset value 0 P P P 0 0 0 0 0 0 RW type RO RO RO RO RO RO RO RO RO RO Type LH - FIFO Current FIFO consumption consumption Table 29. Bit # 15~4 RS1D [0d29, 0x1D]: FIFO control register Name Reserved --Configure the size of the FIFO. Sizes in # of bits: 0000 = 12 1000 = 44 0001 = 16 1001 = 48 0010 = 20 1010 = 52 0011 = 24 1011 = 56 0100 = 28 1100 = 60 0101 = 32 1101 = 64 0110 = 36 0111 = 40 Description Reset value 0 RW type R/W Type 3~0 FIFO size select 0 R/W Table 30. Bit # RS1E [0d30, 0x1E]: Packet counter register Name Packet length counter Description Number of bytes in the last packet received Reset value 0 RW type Type 15~0 RO 35/53 DataSheet 4 U .com www..com Device operation STE101P 7 Device operation The STE101P includes a 10/100 Base-T Ethernet Transceiver with MII, RMII, and SMII interfaces for data and control from/to the Station Management Entity (STE). The STE101P integrates the IEEE802.3u compliant functions of PCS (Physical Coding Sub-layer), PMA (Physical Medium Attachment), and PMD (Physical Medium Dependent) for 100Base-TX, and the IEEE802.3 compliant functions of Manchester encoding/decoding and transceiver for 10Base-T. IEEE standard auto-negotiation functions are also supported. Media Independent Interface (MII) is a 4-bit interface transferring 10Mbit data using a 2.5MHz clock and 100Mbit data using a 25MHz clock. RMII (Reduced Media Independent Interface) is a low pin count alternative capable of transferring 10 and 100 Mbit dibits data using a 50MHz reference clock. A further alternative called SMII (Serial Media Independent Interface) is also possible allowing a further reduction in the number of pins required to connect the PHY to the MAC. SMII is capable of transferring 10 and 100 Mbit serial data using a 125MHz reference clock. All the functions and operation schemes are described in the following sections. 7.1 100Base-TX transmit operation In the 100Base-TX transmission, the device provides the transmission functions of PCS, PMA, and PMD for encoding of MII data nibbles to five-bit code-groups (4B/5B), scrambling, serialization of scrambled code-groups, converting the serial NRZ code into NRZI code, converting the NRZI code into MLT3 code, and then driving the MLT3 code into the category 5 Unshielded Twisted Pair cable through an isolation transformer with the turns ratio of 1.414:1. Data code-groups encoder: In normal MII mode application, the device receives nibble type 4B data via the TxD0~3 inputs of the MII. These inputs are sampled by the device on the rising edge of Tx-clk and passed to the 4B/5B encoder to generate the 5B code-group used by 100Base-TX. Idle code-groups: In order to establish and maintain the clock synchronization, the device needs to keep transmitting signals to the medium. The device will generate Idle code-groups for transmission when there is no real data want to be sent by MAC. Start-of-stream delimiter-SSD (/J/K/): In a transmission stream, the first 16 nibbles are MAC preamble. In order to let partner delineate the boundary of a data transmission sequence and to authenticate carrier events, the device will replace the first 2 nibbles of the MAC preamble with /J/K/ code-groups. End-of-stream delimiter-ESD (/T/R/): In order to indicate the termination of the normal data transmissions, the device will insert 2 nibbles of /T/R/ code-group after the last nibble of FCS. Scrambling: All the encoded data (including the idle, SSD, and ESD code-groups) is passed to the data scrambler to reduce the EMI and spread the power spectrum using a 10bit scrambler seed loaded at the beginning. 36/53 DataSheet 4 U .com www..com STE101P Device operation Data conversion of parallel to serial, NRZ to NRZI, NRZI to MLT3: After scrambled, the transmission data with 5B type in 25MHz will be converted to serial bit stream in 125MHz by the parallel to serial function. After serialized, the transmission serial bit stream will be further converted from NRZ to NRZI format. This NRZI conversion function can be bypassed, if the bit 7 of PR13 register is cleared as 0. After NRZI converted, the NRZI bit stream is passed through MLT3 encoder to generate the TP-PMD specified MLT3 code. With this MLT3 code, it lowers the frequency and reduces the energy of the transmission signal in the UTP cable and also makes the system easily to meet the FCC specification of EMI. Wave-shaper and media signal driver: In order to reduce the energy of the harmonic frequency of transmission signals, the device provides the wave-shaper prior to the line driver to smooth but keep symmetric the rising/falling edge of transmission signals. The wave-shaped signals include the 100Base-TX and 10Base-T both are passed to the same media signal driver. This design can simplify the external magnetic connection with single one. RMII mode: Uses a reference clock (SCLK) of 50MHz. For RMII mode, CRS and RX_DV pins combine their functionality into the CRS_DV pin (pin 48). The CRS_DV pin will toggle at the end of a frame to indicate that the data is being emptied from the internal FIFO's. SMII mode: Uses a reference clock (SCLK) of 125 MHz. Serial data is passed while operating in SMII mode. Only Bit 0 of the txd bus is used to pass the serial frames. The first bit of the frames is identified by the sync pulse. A FIFO is not needed for the transmit data path as the internal 25MHz clock used for the encoding is synchronized with the 125MHz reference clock. 7.2 100Base-TX receive operation In the 100Base-TX receiving operation, the device provides the receiving functions of PMD, PMA, and PCS for receiving incoming data signals through category 5 UTP cable and an isolation transformer with 1.414:1 turns ratio. It includes the adaptive equalizer and baseline wander, data conversions of MLT3 to NRZI, NRZI to NRZ and serial to parallel, the PLL for clock and data recovery, the de-scrambler, and the decoder of 5B/4B. Adaptive equalizer and baseline wander: Since the high speed signals over the unshielded (or shielded) twisted Pair cable will induce the amplitude attenuation and phase shifting. Furthermore, these effects are depends on the signal frequency, cable type, cable length and the connectors of the cabling. So a reliable adaptive equalizer and baseline wander to compensate all the amplitude attenuation and phase shifting are necessary. In the transceiver, it provides the robust circuits to perform these functions. MLT3 to NRZI decoder and PLL for data recovery: After receiving the proper MLT3 signals, the device converts the MLT3 to NRZI code for further processing. After adaptive equalizer, baseline wander, and MLT3 to NRZI decoder, the compensated signals with NRZI type in 125MHz are passed to the Phase Lock Loop circuits to extract out the original data and synchronous clock. Data conversions of NRZI to NRZ and serial to parallel: After data is recovered, the signals will be passed to the NRZI to NRZ converter to generate the 125 MHz serial bit stream. This serial bit stream will be packed to parallel 5B type for further processing. The NRZI to NRZ conversion can be bypassed, if the bit 7 of PR13 register is cleared as 0. De-scrambling and decoding of 5B/4B: The parallel 5B type data is passed to descrambler and 5B/4B decoder to return their original MII nibble type data. 37/53 DataSheet 4 U .com www..com Device operation STE101P Carrier sensing: Carrier Sense (CRS) signal is asserted when the STE101P detects any 2 non-contiguous zeros within any 10 bit boundary of the receiving bit stream. CRS is deasserted when ESD code-group or Idle code-group is detected. In half duplex mode, CRS is asserted during packet transmission or receive. But in full duplex mode, CRS is asserted only during packet reception. RMII mode: 5B code group are converted to 4bit nibbles and the data is sent through a FIFO to the RMII receive data pins as dibits. In case of invalid code group in the data stream, REXER signal is asserted and the 4 bits of the receive data pins will be driven with a specific code signalling the type of error detected. SMII mode: Receive data is buffered in a FIFO to bridge differences between the recovered and reference clocks. Control information and data nibbles are encapsulated into segments of 10 bit SMII frames. Each frame represents a byte of data. The RXER pin is asserted relevant to errant packet data entering the FIFO. 7.3 10Base-T transmit operation In the 10Base-T, the device's TX channel includes the parallel to serial converter, NRZ to Manchester Encoder, Link pulse generation, and an internal Physical Ethernet Wire Interface (Phy). It also provides Collision detection and SQE test for half duplex application. RMII mode: Uses a reference clock (SCLK) of 50 MHz. The value on txd[1:0] must be valid such that txd[1:0] may be sampled every 10th cycle yielding the correct frame data. To achieve this, the dibits should be repeated 10 times. SMII mode: Uses a reference clock (SCLK) of 125MHz. The MII nibbles must be extracted from the SMI frame for sampling on a 2.5MHz clock. To achieve this, the serial txd frame should be repeated 10 times. 7.4 10Base-T receive operation The 10Base-T RX channel contains the Phy, SMART Squelch circuits, clock recovery circuits, Link pulse detector, Manchester-to-NRZ decoder and serial-to-parallel converter. Manchester decoding is performed on the data stream. RMII mode: Dibits are repeated 10 times so that any repeated dibit may be sampled on the 10Mb clock edge. SMII mode: The MII nibbles are extracted from the SMI frame and ready for sampling on a 2.5MHz clock. To allow for this, the serial txd frame is repeated 10 times. 7.5 Loop-back operation The STE101P provides internal loop-back option for both the 100Base-TX and 10Base-T operations. Setting bit 14 of PR00 register to 1 can enable the loop-back option. In this loopback operation, the txp/txn and rxp/rxn lines are isolated from the media. The STE101P also provides remote loop-back operation for 100Base-TX operation. Setting bit 9 of PR13 register to 1 enables the remote loop-back operation. In the 100Base-TX internal loop-back operation, the data comes from the transmit output of NRZ to NRZI converter then loop-back to the receive path into the input of NRZI to NRZ converter. 38/53 DataSheet 4 U .com www..com STE101P Device operation In the 100Base-TX remote loop-back operation, the data is received from rxp/rxn pins through receive path to the output of data and clock recover and then loop-back to the input of NRZI to MLT3 converter of transmit path then transmit out to the medium via the transmit line drivers. In the 10Base-T loop-back operation, the data is through transmit path and loop-back from the output of the Manchester encoder into the input of Phase Lock Loop circuit of receive path. 7.6 Full duplex and half duplex operation The STE101P can operate for either full duplex or half duplex network application. In full duplex, both transmit and receive can be operated simultaneously. Under full duplex mode, collision (COL) signal is ignored and carrier sense (CRS) signal is asserted only when the STE101P is receiving. In half duplex mode, either transmit or receive can be operated at one time. Under half duplex mode, collision signal is asserted when transmit and receive signals collided and carrier sense asserted during transmission and reception. 7.7 Auto-negotiation operation The Auto-Negotiation function is designed to provide the means to exchange information between the STE101P and the network partner to automatically configure both to take maximum advantage of their abilities, and both are setup accordingly. The Auto-Negotiation function can be controlled through ANE, bit 12 of the PR00 register, or the MF0 pin 5. Auto-Negotiation exchanges information with the network partner using the Fast Link Pulses (FLPs) - a burst of link pulses. There are 16 bits of signaling information contained in the burst pulses to advertise all remote partner's capabilities which are determined by the register of PR04. According to this information they find out their highest common capability by following the priority sequence as below: 1. 2. 3. 4. 100Base-TX full duplex 100Base-TX half duplex 10Base-T full duplex 10Base-T half duplex During power-up or reset, if Auto-Negotiation is found enabled then FLPs will be transmitted and the Auto-Negotiation function will proceed. Otherwise, the Auto-Negotiation will not occur until the bit 12 of PR0 register is set to 1. When Auto-Negotiation is disabled, then the Network Speed and Duplex Mode are selected by programming PR00 register. 7.8 Power down operation To reduce the power consumption, the STE101P is designed with a power down feature, which can save the power consumption significantly. Since the power supply of the 100Base-TX and 10Base-T circuits are separated, the STE101P can turn off the circuit of either the 100Base-TX or 10Base-T when the other one of them is operating. There is also a Power Down mode which can be selected by PDEN in register PR00 bit 11. During the Power Down mode, TXP/TXN outputs and all LED outputs are 3-stated, and the MII 39/53 DataSheet 4 U .com www..com Device operation STE101P interface is isolated. During Power Down mode the MII management interface is still available for reading and writing device registers. Power Down mode can be exited by clearing bit 11 of register PR00 or by a hardware or software reset (setting PR00:15=1). 7.9 LED display operation The STE101P provides 5 LED pins, the detail descriptions about the operation are described in the PIN Description section, and as follows. Speed LED: 100Mbps(on) or 10Mbps(off) Receive LED: Blinks at 10Hz when receiving, but not colliding Transmit LED: Blinks at 10Hz when transmitting, but not colliding Link LED: On when 100M or 10M link is active. It will also blink at 10Hz for Transmit and Receive Activity if bit 9 of register PR1B (0x1b) is 0 (default). It will not blink if register PR1B bit 9 = 1. Collision LED: Blinks at 20Hz to indicate a collision 7.10 Reset operation There are two ways to reset the STE101P. First, for hardware reset, the STE101P can be reset via RESET pin (pin 28). The active low Reset input signal is required for at least 1 ms, and at least one transition is required on MDC (pin 42) to ensure proper reset operation. The RIP output pin 29 goes to a logic 1 to indicate that reset has completed. Second, for software reset, when bit 15 of register PR00 is set to 1, the STE101P resets the entire circuits and registers to their default values, then clear the bit 15 of PR00 to 0, and set the RIP output pin 29 to logic 1. Both hardware and software reset operations initialize all registers to their default values. This process includes re-evaluation of all hardware-configurable registers. Logic levels on several I/O pins are detected during hardware reset period to determine the initial functionality of STE101P. Some of these pins are used as outputs after the reset operation. Care must be taken to ensure that the configuration setup will not interfere with normal operation. Dedicated configuration pins can be tied to the Vcc or ground directly. Configuration pins multiplexed with LED outputs should be weakly pulled up or weakly pulled down through resistors as shown in the following circuits. 40/53 DataSheet 4 U .com www..com STE101P Device operation Figure 4. LED connection for Logic level 0 Figure 5. LED connection for Logic level 1 Note: The above LED connections are recommended for setting a Logic Level 1 or Logic Level 0 on the STE101P LED/PHY address pins, for determining PHY address. 7.11 Preamble suppression Preamble suppression mode in the STE101P is indicated by a one in bit six of the PR1 Register. If it is determined that all PHY devices in the system support preamble suppression, then a preamble is not necessary for each management transaction. The first transaction following power-up/hardware reset requires 32 bits of preamble. The full 32 bit preamble is not required for each additional transaction. The STE101P will respond to management accesses without preamble, but a minimum of one idle bit between management transactions is required as specified in IEEE 802.3u. 7.12 Remote fault The remote fault function indicates to a link partner that a fault condition has occurred by using the Remote Fault bit, which is encoded in bit 13 of the Link Code Word. A local device indicates to its link partner that it has found a fault by setting the Remote Fault bit in the Auto-Negotiation register to logic one and renegotiating with the link partner. The Remote Fault bit remains at logic one until successful negotiation with the Link Code Word occurs. The bit will then return to 0. When the message is sent that the Remote Fault bit is set to logic one, the device will set the Remote Fault bit in the MII to logic one if the management function is present. 41/53 DataSheet 4 U .com www..com Device operation STE101P 7.13 Transmit isolation Figure 6. Transmit isolation STA/STE Ethernet ttp STEPHY1 STE101P RxD TxD 4/5 4/5 tpn MII TX(100MHz)/TP(10MHz) The transmit isolation isolates the PHY from MII and Tx +/- interface. As in the Isolate mode, all MII inputs are ignored and all MII outputs are tri-stated. Additionally, all link pulses are suppressed. 7.14 Automatic MDI / MDIX feature The automatic MDI / MDIX feature compensates for using a cross over cable. With Auto MDIX, the STE101P automatically detects what the other device is and switches the TX & RX pins accordingly. The state machine basically controls switching the tdp/tdn and the rdp/rdn signals prior to the auto-negotiation communication. The swapping occurs to allow FLP/NLP to be transmitted and received in the event that the external cable connections have been swapped. 7.15 RMII interface The Reduced Media Independent Interface (RMII) provides a low cost alternative to the IEEE 802.3u MII interface. It can support 10 and 100 Mbit data rates with a single clock, using independent 2 bit wide transmit and receive paths. A single synchronous reference clock (SCLK pin 32) of 50 MHz is used as a timing reference for all transmitters and receivers. By doubling the clock frequency relative to the MII, four pins are saved in the data path, which uses two lines into each transmitter and two lines out of each receiver relative to 4 lines in each direction in the MII interface. Since Start of Packet and End of Packet timing information is preserved across the interface, the MAC is able to derive the COL signal from the receive and transmit data delimiters, saving another pin. 7.16 SMII interface The Serial MII Interface is an alternative to the MII and RMII interfaces to further reduce the number of pins required for the interface from the MAC to the PHY. SMII uses on one data pin (TXD0/RXD0), a SYNC pin, and encodes signals TXER, TXEN, CRS, and RX_DV into the data stream. In SMII mode, the TX_EN pin (54) is used as the SYNC pin for the SMII interface, and a pin 32 (SCLK) requires a reference clock of 125MHz. 42/53 DataSheet 4 U .com www..com STE101P Electrical specifications and timings 8 Table 31. Electrical specifications and timings Absolute maximum ratings Parameter Value -0.5 V to 5.5 V -0.5 V to VCC + 0.5 V -0.5 V to VCC + 0.5 V -65 C to 150 C (-85 F to 302 F) -40 C to +85 C 2000 V V V C (F) C V Unit Supply Voltage(Vcc) Input Voltage Output Voltage Storage Temperature Ambient Temperature ESD Protection Table 32. Symbol General DC Vcc General DC specifications Parameter Test condition Min. Typ. Max. Units Supply voltage 3.15 3.3 3.45 V 10Base-T voltage/current characteristics Vida10 Vidr10 Vod10 Icct10 Idd10 IddA10 Input differential accept peak 5MHz ~ 10MHz voltage Input differential reject peak voltage Output differential peak voltage Line driver supply Digital current consumption Analog current consumption Link active Link active, transmitting 100% 5MHz ~ 10MHz 585 0 2200 17 18 77 3100 585 2800 mV mV mV mA mA mA 100Base-TX voltage/current characteristics Vida100 Vidr100 Vod100 Icct100 Idd100 IddA100 Input differential accept peak voltage Input differential reject peak voltage Output differential peak voltage Line driver supply Digital current consumption Analog current consumption Link active Link active, transmitting 100% 200 0 950 12 25 70 1000 200 1050 mV mV mV mA mA mA 43/53 DataSheet 4 U .com www..com Electrical specifications and timings Table 33. Symbol X1 specifications TX1d TX1p TX1t TX1CL X1 duty cycle X1 period X1 tolerance X1 load capacitance 45 50 30 +/- 50 18 55 STE101P X1 and NLP timing specifications Parameter Test Condition Min. Typ. Max. Units % ns PPM pF 10Base-T normal link pulse (NLP) TNPW TNPC NLP width NLP period 10Mbps 10Mbps 8 100 24 ns ms Figure 7. Normal link pulse timings Tnpw Tnpc Figure 8. Fast link pulse timing Tflcpp Tflcpd Tflpw Tflbw Tflbp 44/53 DataSheet 4 U .com www..com STE101P Table 34. Symbol Tflpw Tflcpp Tflcpd Tflbw Tflbp FLP width Clock pulse to clock pulse period Clock pulse to data pulse period Number of pulses in one burst Burst width FLP burst period Electrical specifications and timings Fast link pulse (FLP) AC timing specifications Parameter Test conditions Min. Typ. 100 111 55.5 17 2 8 16 24 125 62.5 139 69.5 33 Max. Units ns s s pulse ms ms Figure 9. MII management clock timing t1 MDC t4 MDIO(I) t6 MDIO(O) t5 t2 t3 Table 35. Symbol Mll management and 100Base-TX transmitter AC timing specifications Parameter Test conditions Min. Typ. Max. Units MII management clock t1 t2 t3 t4 t5 t6 MDC low pulse width MDC high pulse width MDC period MDIO(I) setup to MDC rising edge MDIO(O) hold time from MDC rising edge MDIO(O) valid from MDC rising edge 200 200 400 10 10 0 -- -- -- -- -- 300 ns ns ns ns ns ns 100Base-TX transmitter Tjit TTLAT TDP-TDN differential output peak jitter Transmit latency - Data on txp/txn after txen asserted 225 1.4 ns ns 45/53 DataSheet 4 U .com www..com Electrical specifications and timings Figure 10. MII receive timing STE101P Table 36. Symbol MII receive t1 t2 Mll receive and 100Base-TX AC timing specifications Parameter Test Condition Min. Typ. Max. Units RX-ER, RX-DV, RXD[3:0] setup to RX-CLK RX-ER, RX-DV, RXD[3:0] hold after RX-CLK RX-CLK high pulse width (100 Mbits/s) RX-CLK high pulse width (10 Mbits/s) RX-CLK low pulse width (100 Mbits/s) 10 10 14 200 14 200 40 400 -- -- 26 ns ns ns ns t3 26 ns ns ns ns t4 RX-CLK low pulse width (10 Mbits/s) RX-CLK period (100 Mbits/s) t5 RX-CLK period (10 Mbits/s) 100Base-TX receiver TRLAT Receive latency -RXDV asserted after valid data on rxp/rxn 225 ns Figure 11. MII transmit timing 46/53 DataSheet 4 U .com www..com STE101P Table 37. Symbol MII Transmit t1 t2 TX-ER,TX-EN,TXD[3:0] Setup to TXCLK Rise TX-ER,TX-EN,TXD[3:0] Hold After TXCLK Rise Electrical specifications and timings MII transmit and 100Base-TX transmitter AC timing specifications Parameter Test Condition Min. Typ. Max. Units 10 0 -- 25 ns ns 100Base-TX transmitter Tjit TTLAT TDP-TDN Differential Output Peak-toPeak Jitter Transmit latency - Data on txp/txn after txen asserted 225 1.4 ns ns Table 38. Symbol TSCLK TSCLK Tsu THOLD TOUT TRLAT TTLAT RMII AC timing specifications Parameter SCLK Frequency SCLK Cycle Time TXD[1:0], TX_EN, TX_ER Setup to SCLK rising edge TXD[1:0], TX_EN, TX_ER Hold after SCLK rising edge RXD[1:0], CRSDV, RX_ER output delay from SCLK rising edge Receive Latency -RXDV asserted after valid data on rxp/rxn Transmit latency - Data on txp/txn after txen asserted 4 2 2 200 300 16 Test Condition Min. Typ. 50 20 Max. Units MHz ns ns ns ns ns ns Figure 12. RMII transmit timing 47/53 DataSheet 4 U .com www..com Electrical specifications and timings Figure 13. RMII receive timing STE101P Table 39. Symbol TSCLK TSCLK Tsu THOLD TOUT TRLAT TTLAT SMII AC timing specifications(1) Parameter SCLK Frequency SCLK Cycle Time TXD0, SYNC Setup to SCLK rising edge TXD0, SYNC Hold after SCLK rising edge RXD0 output delay from SCLK rising edge Receive Latency - CRS after valid data on rxp/rxn Transmit latency - Data on txp/txn after txs/syc 1.5 1 1.5 250 250 5 Test Condition Min. Typ. 125 8 Max. Units MHz ns ns ns ns ns ns 1. The MAC should continuously generate a pulse on SYNC every 10 clocks. Transmit and receive data and control information are provided in ten bit segments. In 10MBit mode, each segment is repeated ten times, so every ten segments represent a new byte of data. Therefore in receive mode the MAC can sample any one of every 10 segments in 10Mbps mode. However in transmit mode the MAC must repeat the data for each of the repeated 10 segments in 10Mbps mode. In SMII mode, the TX_EN pin (54) is used as the SYNC pin for the SMII interface. SLCK is pin 32. For SMII mode the configuration pin setting must be CF2 = 1, CFG1 = 0, CFG0 = 0 48/53 DataSheet 4 U .com www..com STE101P Figure 14. SMII transmit timing Electrical specifications and timings Figure 15. SMII receive timing 49/53 DataSheet 4 U .com www..com Package mechanical data STE101P 9 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 16. TQFP 64 package mechanical drawing 50/53 DataSheet 4 U .com www..com STE101P Table 40. Package mechanical data TQFP 64L/Body 10 x 10 x 1.40 mm / footprint 1.00 mm Dimensions (mm) Reference Min. A A1 A2 B c D D1 D3 e E E1 E3 L L1 K 11.90 9.975 7.450 0.450 11.90 9.975 7.450 0.450 0.938 1.5d 1.000 3.5d 1.063 5.5d 12.00 10.00 7.500 0.500 12.00 10.00 7.500 1.420 0.065 1.360 0.175 0.100 1.400 0.200 Typ. Max. 1.540 0.135 1.440 0.225 0.165 12.10 10.025 7.550 0.550 12.10 10.025 7.550 0.469 0.393 0.293 0.018 0.469 0.393 0.293 0.018 0.037 1.5d 0.039 3.5d 0.042 5.5d 0.472 0.394 0.295 0.020 0.472 0.394 0.295 Min. 0.056 0.003 0.054 0.007 0.004 0.055 0.008 Typ. Max. 0.061 0.005 0.057 0.009 0.006 0.476 0.395 0.297 0.022 0.476 0.395 0.297 Dimensions (inch) 51/53 DataSheet 4 U .com www..com Ordering information STE101P 10 Ordering information Table 41. Order codes Temp range, C -40 to 85 Package TQFP64 (14x14x1.4mm) Packing Tube Part number E-STE101P(1) 1. E-: ECOPACK(R) 11 Revision history Table 42. Date 15-Sep-2006 Document revision history Revision 1 Initial release. Changes 52/53 DataSheet 4 U .com www..com STE101P Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST'S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER'S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. (c) 2006 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 53/53 DataSheet 4 U .com |
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